This paper presents a front-end application-specific integrated circuit (ASIC) that demonstrates the feasibility of inprobe digitization for next-generation miniature 3-D ultrasound probes with acceptable power- and area-efficiency. The proposed design employs a low-power charge-domain ADC that is directly merged with the sample-and-hold delay lines in each subarray, and high-speed datalinks at the ASIC periphery to realize an additional channel-count reduction compared to prior work based on analog subarray beamforming. The 4.8 × 2 mm2 ASIC, which has a compact layout element-matched to a 5-MHz 150-μm-pitch PZT matrix transducer, achieves an overall 36-fold channel-count reduction and a state-of-the-art power-efficiency with less than 1 mW/element power dissipation while receiving, which is acceptable even when scaled up to a 1000-element probe. The prototype ASIC has been fabricated in a 0.18 μm CMOS process. Its functionality has been successfully evaluated with both electrical and acoustical measurements.

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2017 IEEE International Ultrasonics Symposium, IUS 2017
Department of Biomedical Engineering

Chen, C., Chen, Z., Bera, D., Noothout, E., Chang, Z. Y., Vos, R., … Pertijs, M. (2017). A front-end ASIC for miniature 3-D ultrasound probes with in-probe receive digitization. In IEEE International Ultrasonics Symposium, IUS. doi:10.1109/ULTSYM.2017.8091913