This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.

Additional Metadata
Keywords 3-D ultrasound imaging, matrix transducer arrays, sub-array beamforming, transesophageal echocardiography (TEE), ultrasound application-specific integrated circuit (ASIC)
Persistent URL dx.doi.org/10.1109/JSSC.2016.2638433, hdl.handle.net/1765/108449
Journal IEEE Journal of Solid-State Circuits
Citation
Chen, C, Chen, Z, Bera, D, Raghunathan, S.B, Shabanimotlagh, M, Noothout, E, … Pertijs, M.A.P. (2017). A Front-End ASIC with Receive Sub-array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography. IEEE Journal of Solid-State Circuits, 52(4), 994–1006. doi:10.1109/JSSC.2016.2638433