A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes
This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.
|Keywords||ADC, ASIC, receiver, ultrasound|
|Persistent URL||dx.doi.org/10.23919/VLSIC.2019.8778200, hdl.handle.net/1765/120567|
|Conference||33rd Symposium on VLSI Circuits, VLSI Circuits 2019|
Li, J. (Jing), Chen, Z, Tan, M, Van Willigen, D. (Douwe), Chen, C, Chang, Z, … Pertijs, M.A.P. (2019). A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. C220–C221). doi:10.23919/VLSIC.2019.8778200