2016-09-21
A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography
Publication
Publication
Presented at the
30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 (June 2016), Honolulu
This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.
| Additional Metadata | |
|---|---|
| doi.org/10.1109/VLSIC.2016.7573470, hdl.handle.net/1765/93688 | |
| 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 | |
| Organisation | Department of Biomedical Engineering |
|
Chen, C., Chen, Z., Bera, D., Raghunathan, S. B., Shabanimotlagh, M., Noothout, E., … Pertijs, M. (2016). A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. doi:10.1109/VLSIC.2016.7573470 |
|